1. Field of the Invention
The present invention relates to a test circuit, a pattern generating apparatus, and a pattern generating method.
2. Description of Related Art
In these years, as test target circuits are becoming increasingly higher in function, the data amount of internal signal patterns used to verify the operations of the circuits is increasing. The increase in the data amount of internal signal patterns causes the test process for semiconductor integrated circuits (such as LSIs (large scale integrated circuits)) to take a longer time, thus decreasing efficiency in the production of the semiconductor integrated circuits. Note that the internal signal pattern is a set of digital signals arranged in parallel and that the data amount of internal signal patterns is calculated by multiplying the number of rows of internal signal patterns (or the number of internal signal patterns) with the number of digital signals included in the internal signal pattern.
In order to efficiently input internal signal patterns into a test target circuit, i.e., a semiconductor integrated circuit, the semiconductor integrated circuit may be provided with a corresponding number of external terminals to the number of signals of the internal signal pattern, through which terminals internal signal patterns are sequentially input into the semiconductor integrated circuit. However, it is not realistic to provide a corresponding number of external test terminals to a very large number of signals of the internal signal pattern.
Here, the technique related to the reduction in the number of terminals described in the Japanese Unexamined Patent Application Publication No. 4-274547 (hereinafter called reference 1) will be described with reference to FIG. 74. In this reference, by transferring data sequentially over a plurality of times, the number of input/output pins of LSI circuits is reduced. A selector 120 selects data to be transferred based on a select signal. A selector 130 selects either the high-order bit group or the low-order bit group of the data selected by the selector 120. Then, the high-order bit group from the selector 130 is selected as a high-order bit group of a selector/register 170, and the low-order bit group from the selector 130 is selected as a low-order bit group of the selector/register 170.
In Japanese Patent Publication No. 3343734, a trace data compressing method to improve the efficiency in the use of a trace buffer is described.
By utilizing the technique described in reference 1, the number of terminals of a semiconductor integrated circuit can be reduced. However, the data amount of patterns (signal sets of digital signals arranged in parallel) to be input to and output from terminals of the semiconductor integrated circuit, in itself, does not change. That is, with the prior art, in itself the data amount of patterns to be input to and output from terminals of semiconductor integrated circuits cannot be reduced.